1. Field of the Invention
This invention relates to a packet processor for performing predetermined processing on an input packet and outputting the processed packet, a packet control method implemented by this packet processor, and a packet control program for implementing the packet control method. This invention in particular relates to a packet processor having one or two or more packet processing units and designed to supply a clock of a predetermined frequency to each of the packet processing units, a packet control method implemented by this packet processor, and a packet control program for implementing the packet control method.
2. Description of the Related Art
Various energy saving measures are being studied and developed at the global level for the purpose of global environment protection. In this trend, many countries have begun to discuss about enactment of legislation to mandate energy saving and reduction of carbon-dioxide emissions.
In general, many people will think that such energy saving measures apply to energy consumption arising from fields of transportation, logistics, and manufacture. On the other hand, also attracting attention is the increase in energy consumption by electronic equipment such as computers and servers, and information communication equipment and network infrastructure.
In the case of electronic equipment such as computers and servers, a relatively long period of time is spent without arithmetic processing, in other words, the equipment remains in the so-called stand-by state for a relatively long period of time. Therefore, reduction of the power consumption during the stand-by state effectively helps reducing the average power consumption, and hence reducing the carbon-dioxide emissions.
As for information communication equipment, however, such equipment is required to constantly stay in the data communicable state even though the communication system has been changed from analog to digital. Therefore, unlike the electronic equipment such as computers and servers, the stand-by state is prerequisitely not allowable for the information communication equipment.
It is believed, therefore, that the average power consumption of the information communication equipment cannot be reduced unless the stationary operating power is reduced.
As a result, the effort of power reduction is mainly pursued from the viewpoint of device technologies aiming at reduction of the operating voltage accompanied by the increased degree of integration and miniaturization of electronic components.
However, the operating voltage of such electronic components has already been reduced to below one volt. In an actual trend, the extent of reduction of operating voltage due to miniaturization of electronic components is now being decreased, and so is the effect obtained by increased degree of integration.
This has made it difficult to achieve significant reduction of power consumption, only by miniaturization or increased degree of integration of electronic components.
Advanced miniaturization of electronic components (for example, below 90 nm) has increased the leaked current up to a considerable level. For this reason, the power consumption during the stand-by state is being significantly increased in spite of research efforts made by device vendors using the device technologies.
On the other hand, various researches are being made also from the viewpoint of circuitry designs.
In this connection, efforts to reduce the power consumption are slowly but progressively pursued by employing an asynchronous circuit architecture and method using no clocks in place of a clock synchronization circuit architecture and method currently mainly used in designing internal circuit configuration of electronic components.
This technique aims to reduce the average power consumption by reducing the stationary operating power and the power consumption during the stand-by state. However, special development tools are required for design and verification in order to employ such asynchronous circuit architecture and method for common electronic components such as ASICs (Application Specific Integrated Circuits) and FPGAs (Field Programmable Gate Arrays). Such development tools have not yet been developed to such an extent as to be accessible for developers in general.
There are known several types of packet processors which perform a plurality of processing operations depending on content of a received packet and output the packet after completing all the processing operations. One of these packet processors is described, for example, in Japanese Laid-Open Patent Publication NO. 2002-164924.
These types of packet processors have a plurality of packet processing units. Each of these packet processing units is constantly supplied with a clock regardless of whether or not it has a packet to process. Therefore, considerably large power is, consumed when no packet is processed.
On the other hand, there are also known wireless communication devices designed to process a received signal by a plurality of processing units in sequence. This type of wireless communication device is described in Japanese Laid-Open Patent Publication NO. 2004-236350, for example.
In such a wireless communication device, a preceding processing unit monitors whether or not there exists data to be processed by a subsequent processing unit. The clock supply to the subsequent processing unit is controlled based on a monitoring result. In this manner, the wireless communication device is allowed to reduce the power consumption according to the amount of data to be processed.
However, this wireless communication device is only capable of dealing with received signals having a specific frame configuration, and is not capable of processing variable-length packets or responding to variation in processing time in the processing units. Consequently, the technology of this wireless communication device is not applicable directly to packet processors.